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1 datasheet 2.048v radiation hardened ultra low noise, precision voltage reference isl71091seh20 the isl71091seh20 is an ultra low noise, high dc accuracy precision voltage reference with a wide input voltage range from 4.2v to 30v. it uses intersil?s advanced bipolar technology to achieve 3.8v p-p 0.1hz to 10hz noise with an initial voltage accuracy of 0.05%. the isl71091seh20 offers a 2.048v output voltage option with 6ppm/c temperature coefficient and also provides excellent line and load regulation . the device is offered in an 8 ld flatpack package. the isl71091seh20 is ideal for high-end instrumentation, data acquisition and processing applications requiring high dc precision where low noise performance is critical. applications ? precision voltage sources for data acquisition system for space application ? strain and pressure gaug e for space applications ? radiation hardened pwm requiring precision outputs related literature ? an1906 , ?isl71091sehxxev1z user?s guide? ? an1938 , ?single event effects (see) testing of the isl71091sehxx precision voltage references family? ? an1939 , ?total dose testing of the isl71091sehxx precision voltage reference? features ? reference output voltage . . . . . . . . . . . . . . . .2.048v 0.05% ? accuracy over temperature . . . . . . . . . . . . . . . . . . . . . 0.15% ? accuracy over radiation . . . . . . . . . . . . . . . . . . . . . . . . 0.25% ? output voltage noise . . . . . . 3.8v p-p typical (0.1hz to 10hz) ? supply current . . . . . . . . . . . . . . . . . . . . . . . . . 300a (typical) ?v os temperature coefficient . . . . . . . . . . 6ppm/c maximum ? output current capability . . . . . . . . . . . . . . . . . . . 10ma/-5ma ? line regulation . . . . . . . . . . . . . . . . . . . . . . 5ppm/v maximum ? load regulation (sourcing) . . . . . . . . . 40ppm/ma maximum ? operating temperature range. . . . . . . . . . . .-55c to +125c ? radiation environment - high dose rate (50 to 300rad(si)/s) . . . . . . . . . 100krad(si) - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . 100krad(si)* - sel/seb free (v cc = 36v) . . . . . . . . . . . . 86mev?cm 2 /mg *product capability established by initial characterization. the ?eh? version is acceptance tested on a wafer-by-wafer basis to 50krad(si) at low dose rate. ? electrically screened to smd 5962-14208 figure 1. isl71091seh20 typical application diagram figure 2. v out vs temperature 0.1f vee vdd refin vdd bipoff vee dacout gnd vin vref 1f d0 hs-565brh 1 2 3 4 6 8 7 5 isl71091seh20 d12 1.1k c note: select c to minimize settling time. dnc vin comp gnd dnc dnc vout trim 1nf 2.045 2.046 2.047 2.048 2.049 2.050 2.051 -65 -45 -25 -5 15 35 55 75 95 115 135 unit 1 unit 3 unit 2 unit 4 unit 5 temperature (c) v out (v) march 17, 2016 fn8632.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014, 2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl71091seh20 2 fn8632.2 march 17, 2016 submit document feedback ordering information ordering number ( notes 1 , 2 ) part number v out option ( note 3 ) (v) grade (%) tempco (ppm/c) temp range (c) package (rohs compliant) pkg. dwg. # 5962r1420801vxc isl71091sehvf20 2.048 0.05 6 -55 to +125 8 ld flatpack k8.a 5962r1420801v9a isl71091sehvx20 2.048 0.05 6 -55 to +125 die isl71091sehf20/proto isl71091sehf20/proto 2.048 0.05 6 -55 to +125 8 ld flatpack k8.a isl71091sehx20sample isl71091sehx20sample 2.048 0.05 6 -55 to +125 die isl71091seh20ev1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ?ordering information? table must be used when ordering. 3. for alternate v out options, visit the isl71090seh and isl71091seh family pages. table 1. key differences between family of parts part v out ? (v) tempco (ppm/c) output voltage noise (v p-p ) load regulation (ppm/ma) isl71091seh20 2.048 6 3.8 40 isl71091seh333.365.225 ISL71091SEH40 4.096 6 6.2 20 isl71091seh10 10 6 14.8 15
isl71091seh20 3 fn8632.2 march 17, 2016 submit document feedback pin configuration isl71091seh20 (8 ld flatpack) top view 8 7 6 5 2 3 4 1 dnc vin comp gnd dnc dnc vout trim note: the esd triangular mark is indicative of pin #1. it is part of the device marking and is placed on the lid in the quadrant where pin #1 is located. pin descriptions pin number pin name esd circuit description 1, 7, 8 dnc 3 do not connect. internally terminated. 2vin1input voltage connection. 3 comp 2 compensation and noise reduction capacitor. 4 gnd 1 ground connection. also connected to the lid. 5 trim 2 voltage reference trim input. 6 vout 2 voltage reference output. vdd capacitively trigger clamp gnd vdd gnd pin vdd nc esd circuit 1 esd circuit 2 esd circuit 3
isl71091seh20 4 fn8632.2 march 17, 2016 submit document feedback functional block diagram figure 3. functional block diagram comp gnd vout trim dnc dnc dnc vin gm 1.2v 1.2v 3.7v bias regulator typical trim application diagram figure 4. typical trim application diagram 1m vin vref 1f 1 2 3 4 6 8 7 5 isl71091seh20 dnc vin comp gnd dnc dnc vout trim 1nf 10k 0.1f
isl71091seh20 5 fn8632.2 march 17, 2016 submit document feedback absolute maximum rating s thermal information maximum voltage vin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +40v vin to gnd at an let = 86mev?cm 2 /mg . . . . . . . . . . . . . . -0.5v to +36v vout to gnd (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5v to v out + 0.5v voltage on any pin to ground . . . . . . . . . . . . . . . . . . . -0.5v to +v out + 0.5v voltage on dnc pins. . . . . . . . . . . . . . . no connections permitted to these pins esd ratings (mil std 883 method) human body model (tested per mil-prf-883 3015.7). . . . . . . . . . . 2kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101d) . . . . . . . . . . . 750v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 8 ld flatpack package ( notes 4 , 5 ). . . . . . 135 11 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (t jmax ) . . . . . . . . . . . . . . . . . . . . .+150c recommended operating conditions input voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.2v to +30v ambient operating temperature range . . . . . . . . . . . . . -55c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 5. for ? jc , the ?case temp? location is the center of the ceramic on the package underside. electrical specific ations for flatpack v in = 5v, i out = 0ma, c l = 1f and c comp = 0.001f unless otherwise specified. boldface limits apply after radiation at +25c and ac ross the operating temperature range, -55c to +125c without radiation, unless oth erwise specified. parameter description test conditions min ( note 6 )typ max ( note 6 )unit v out output voltage 2.048 v v oa v out accuracy at t a = +25c v out = 2.048v ( note 9 ) -0.05 +0.05 % v out accuracy at t a = -55c to +125c v out = 2.048v ( note 9 ) -0.15 +0.15 % v out accuracy at t a = +25c, post radiation v out = 2.048v ( note 9 ) -0.25 +0.25 % tc v out output voltage temperature coefficient ( note 7 ) 6 ppm/c v in input voltage range v out = 2.048v 4.2 30.0 v i in supply current 0.3 0.5 ma ? v out / ? v in line regulation v in = 4.2v to 30v, v out = 2.048v 0.3 5 ppm/v ? v out / ? i out load regulation sourcing: 0ma i out 10ma 11 40 ppm/ma sinking: -5ma i out 0ma 25 80 ppm/ma v d dropout voltage ( note 8 )i out = 10ma 2 2.5 v i sc+ short-circuit current t a = +25c, v out tied to gnd 55 ma i sc- short-circuit current t a = +25c, v out tied to v in -61 ma t r turn-on settling time 90% of final value, c l = 1.0f, c c = 1000pf 344 s psrr ripple rejection f = 120hz 90 db e n v p-p output voltage noise 0.1hz f ? 10hz, v out = 2.048v 3.8 v p-p e n v rms broadband voltage noise 10hz f 1khz, v out = 2.048v 3.4 v rms e n noise density f = 1khz, v out = 2.048v 91 nv/ hz ? v out / ? t long term stability t a = +25c, 1000 hours 20 ppm
isl71091seh20 6 fn8632.2 march 17, 2016 submit document feedback electrical specif ications for die v in = 5v, i out = 0, c l = 1f and c comp = 0.001f unless otherwise specified. boldface limits apply after radiation at +25c and across the operating temperature range, -55c to +125c without radi ation, unless otherwise specified. specifications over temperature are guaranteed but not production tested on die. parameter description conditions min ( note 6 )typ max ( note 6 )unit v out output voltage 2.048 v v oa v out accuracy at t a = +25c v out = 2.048v ( note 10 ) -0.05 +0.05 % v out accuracy at t a = -55c to +125c v out = 2.048v ( note 10 ) -0.15 +0.15 % v out accuracy at t a = +25c, post radiation v out = 2.048v ( note 10 ) -0.25 +0.25 % tc v out output voltage temperature coefficient ( note 7 ) 6 ppm/c v in input voltage range v out = 2.048v 4.2 30.0 v i in supply current 0.3 0.5 ma ? v out / ? v in line regulation v in = 4.2v to 30v 0.3 5 ppm/v ? v out / ? i out load regulation sourcing: 0ma i out 10ma 11 40 ppm/ma sinking: -5ma i out 0ma 25 80 ppm/ma v d dropout voltage ( note 8 )i out = 10ma 2.0 2.5 v notes: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. over the specified temperature range. temperature coefficien t is measured by the box method whereby the change in v out is divided by the temperature range; in this case, -55c to +125c = +180c. 8. dropout voltage is the minimum v in - v out differential voltage measured at the point where v out drops 1mv from v in = nominal at t a = +25c. 9. post-reflow drift for the isl71091seh20 devices can exceed 100v based on experimental results with devices on fr4 double-sid ed boards. the engineer must take this into account when co nsidering the reference voltage after assembly. 10. the v out accuracy is based on die mount with silver glass die attach mate rial such as ?qmi 2569? or equivalent in a package with an alu mina ceramic substrate.
isl71091seh20 7 fn8632.2 march 17, 2016 submit document feedback total dose radiation characteristics this data is typical mean test data post total dose radiation exposure at both low dose rate (ldr) of <10mrad(si)/s to 50krads and at a high dose rate (hdr) of 50 to 300rad(si)/s to 150krads. this d ata is intended to show typical parameter shifts due to low dose ra te radiation. these are not limits nor are they guaranteed. ldr data to 150krads wil l be added when available. v in = 5v, t a = +25c, i out = 0, c in = 0.1f, c l = 1f and c comp = 0.001f unless otherwise specified. figure 5. v out accuracy shift figure 6. supply current shift figure 7. line regulation shift figure 8. load regulation (sourcing) shift figure 9. load regulation (sinking) shift figure 10. dropout shift 2.042 2.044 2.046 2.048 2.050 2.052 2.054 0 50 100 150 anneal spec limit spec limit ldr bias ldr gnd hdr bias hdr gnd total dose (krad (si)) v out (v) 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0 50 100 150 anneal i in ( ma) total dose (krad (si)) spec limit spec limit ldr bias ldr gnd hdr gnd hdr bias -6 -4 -2 0 2 4 6 0 50 100 150 anneal total dose (krad (si)) spec limit ldr bias ldr gnd hdr bias hdr gnd spec limit line regulation (ppm/v) -50 -40 -30 -20 -10 0 10 20 30 40 50 0 50 100 150 anneal total dose (krad (si)) load regulation (ppm/ma) spec limit spec limit ldr bias ldr gnd hdr bias hdr gnd -100 -80 -60 -40 -20 0 20 40 60 80 100 0 50 100 150 anneal spec limit spec limit ldr gnd hdr bias hdr gnd total dose (krad (si)) load regulation (ppm/ma) ldr bias 0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 150 dropout (v) total dose (krad (si)) spec limit ldr bias ldr gnd hdr gnd anneal hdr bias
isl71091seh20 8 fn8632.2 march 17, 2016 submit document feedback typical performance curves v in = 5v, t a = +25c, i out = 0, c in = 0.1f, c l = 1f and c comp = 0.001f, unless otherwise specified. figure 11. line regulation vs v out (v) over temperature figure 12. line regulation vs ? v out (ppm) over temperature figure 13. load regulation vs v out (v) over temperature figure 14. load regulation vs v out (ppm) over temperature figure 15. dropout voltage vs output current figure 16. v out vs temperature 2.0460 2.0465 2.0470 2.0475 2.0480 2.0485 2.0490 2.0495 2.0500 4.2 7.4 10.7 13.9 17.1 20.3 23.6 26.8 30.0 v out (v) v in (v) -55c +125c +25c -20 -15 -10 -5 0 5 10 15 20 4.2 7.4 10.7 13.9 17.1 20.3 23.6 26.8 30.0 v in (v) ? v out (ppm) +25c +125c -55c 2.0460 2.0465 2.0470 2.0475 2.0480 2.0485 2.0490 2.0495 2.0500 -5.0 -2.5 0 2.5 5.0 7.5 10 sinking i load (ma) sourcing v out (v) +125c -55c +25c -500 -400 -300 -200 -100 0 100 200 300 400 500 -5.0 -2.5 0 2.5 5.0 7.5 10.0 sinking i load (ma) sourcing load regulation (ppm) +125c -55c +25c 0 0.5 1.0 1.5 2.0 2.5 024681012 i load (ma) dropout (v) +125c -55c +25c 2.045 2.046 2.047 2.048 2.049 2.050 2.051 -65 -45 -25 -5 15 35 55 75 95 115 135 unit 1 unit 3 unit 2 unit 4 unit 5 temperature (c) v out (v)
isl71091seh20 9 fn8632.2 march 17, 2016 submit document feedback figure 17. i in vs v in over temperature figur e 18. line transient ( ? v in = 500mv) figure 19. load transient ( ? i l = 1ma) figure 20. turn-on time figure 21. ripple rejection vs frequency fig ure 22. noise voltage density vs frequency typical performance curves v in = 5v, t a = +25c, i out = 0, c in = 0.1f, c l = 1f and c comp = 0.001f, unless otherwise specified. (continued) 0 0.1 0.2 0.3 0.4 0.5 0.6 4.2 7.4 10.7 13.9 17.1 20.3 23.6 26.8 30.0 v in (v) i in (ma) -55c +25c +125c -4 -3 -2 -1 0 1 2 3 4 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) amplitude (mv) v out -80 -60 -40 -20 0 20 40 60 80 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) amplitude (mv) v out -1 0 1 2 3 4 5 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v in v out amplitude (v) time (ms) -120 -100 -80 -60 -40 -20 0 10 100 1k 10k 100k 1m 10m frequency (hz) psrr (db) c in = 0 ? v in = 1v p-p 10 100 1000 10000 1 10 100 1k 10k 100k frequency (hz) voltage noise (nv/hz)
isl71091seh20 10 fn8632.2 march 17, 2016 submit document feedback figure 23. v out vs noise, 0.1hz to 10hz typical performance curves v in = 5v, t a = +25c, i out = 0, c in = 0.1f, c l = 1f and c comp = 0.001f, unless otherwise specified. (continued) -10 -8 -6 -4 -2 0 2 4 6 8 10 012345678910 time (s) output noise voltage (v)
isl71091seh20 11 fn8632.2 march 17, 2016 submit document feedback device operation bandgap precision references the isl71091seh20 uses a bandgap architecture and special trimming circuitry to produce a temperature compensated, precision voltage reference with high input voltage capability and moderate output current drive. applications information board mounting considerations for applications requiring the hi ghest accuracy, board mounting location should be reviewed. the device uses a ceramic flatpack package. generally mild stresse s to the die when the printed circuit (pc) board is heated and cooled, can slightly change the shape. because of these die stresse s, placing the device in areas subject to slight twisting can cause degradation of reference voltage accuracy. it is normally be st to place the device near the edge of a board, or on the shortest side, because the axis of bending is most limited in that location. mounting the device in a cutout also minimizes flex. obvi ously, mounting the device on flexprint or extremely thin pc material will likewise cause loss of reference accuracy. board assembly considerations some pc board assembly prec autions are necessary. normal output voltage shifts of 100v to 500v can be expected with pb-free reflow profiles or wave solder on multilayer fr4 pc boards. precautions should be ta ken to avoid excessive heat or extended exposure to high reflow or wave solder temperatures. noise performance and reduction the output noise voltage in a 0.1h z to 10hz bandwidth is typically 3.8v p-p (v out = 2.048v). the noise meas urement is made with a bandpass filter. the filter is made of a 1-pole high-pass filter, with a corner frequency at 0.1hz, and a 2-pole low-pass filter, with a corner frequency (3db) at 9.9hz, to create a filter with a 9.9hz bandwidth. noise in the 10hz to 1khz bandwidth is approximately 3.4v rms (v out = 2.048v), with 0.1f capacitance on the output. this noise measurement is made wi th a 2 decade bandpass filter. the filter is made of a 1-pole high-pass filter with a corner frequency at 10hz of the center frequency, and 1-pole low-pass filter with a corner frequency at 1khz. load capacitance up to 10f can be added but will result in only marginal improvements in output noise and transient response. turn-on time normal turn-on time is typically 344s, as shown in figure 20 on page 9 . the circuit designer must take this into account when looking at power-up delays or sequencing. temperature coefficient the limits stated for temperature coefficient (tempco) are governed by the method of measurement. the overwhelming standard for specifying the temperature drift of a reference is to measure the reference voltage at two temperatures. take the total variation, (v high ? v low ), and divide by the temperature extremes of measurement (t high ?t low ). the result is divided by the nominal reference voltage (at t = +25c) and multiplied by 10 6 to yield ppm/c. this is the ?box? method for specifying temperature coefficient. output voltage adjustment the output voltage can be adjusted above and below the factory-calibrated value via the trim terminal. the trim terminal is the negative feedback divider point of the output op amp. the voltage at the trim pin is set at approximately 1.216v by the internal bandgap and amplifier circuitry of the voltage reference. the suggested method to adjust the output is to connect a very high value external resistor directly to the trim terminal and connect the other end to the wipe r of a potentiometer that has a much lower total resistance and whose outer terminals connect to v out and ground. it is important to minimize the capacitance on the trim terminal to preserve output amplifier stability. it is also best to connect the series resistor directly to the trim terminal, to minimize that capa citance and also to minimize noise injection. small trim adjustments, such as 0.25%, will not disturb the factory-set temperature coefficient of the reference, but trimming by large amounts can. output stage the output stage of the device ha s a push-pull configuration with a high-side pnp and a low-side npn. this helps the device to act as a source and sink. the devi ce can source 10ma and sink 5ma. use of comp capacitors the reference can be compensated for the c out capacitors used by adding a capacitor from the comp pin to gnd. see table 2 for recommended values of the comp capacitor. data from see testing suggests the best option to use is 1f for c out and 1nf for c comp . refer to the see report ( an1938 ) for more details. dnc pins these pins are for trimming purposes and for factory use only. do not connect these to the circuit in any way. it will adversely effect the performance of the reference. simulation model a spice simulation model is available under the documents tab of the isl71091seh20 landing page on the intersil website. figures 24 through 29 show a comparison of the characterized part performance and the simulated part performance. table 2. c out (f) c comp (nf) 0.1 1 11 10 10
isl71091seh20 12 fn8632.2 march 17, 2016 submit document feedback characterization vs simulation results figure 24. simulated (worse case) v out vs temperature figure 25. characterized v out vs temperature figure 26. simulated line transient ( ? v in = 500mv) figure 27. characterized line transient ( ? v in = 500mv) figure 28. simulated load transient ( ? i l = 1ma) figure 29. characterized load transient ( ? i l = 1ma) 2.045 2.046 2.047 2.048 2.049 2.050 2.051 -65 -45 -25 -5 15 35 55 75 95 115 135 temperature (c) v out (v) 2.045 2.046 2.047 2.048 2.049 2.050 2.051 -65 -45 -25 -5 15 35 55 75 95 115 135 unit 1 unit 3 unit 2 unit 4 unit 5 temperature (c) v out (v) 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.045 2.046 2.047 2.048 2.049 2.050 2.051 2.044 2.052 time (ms) amplitude (v) v out -4 -3 -2 -1 0 1 2 3 4 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) amplitude (mv) v out 0 0.250.500.751.001.251.501.752.00 1.987 2.007 2.028 2.048 2.069 2.089 2.109 1.968 2.128 time (ms) amplitude (v) v out -80 -60 -40 -20 0 20 40 60 80 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 time (ms) amplitude (mv) v out
isl71091seh20 13 fn8632.2 march 17, 2016 submit document feedback package characteristics weight of packaged device 0. 31 grams (typical) lid characteristics finish: gold potential: connected to pin #4 (gnd) case isolation to any lead: 20 x 10 9 (minimum) die characteristics die dimensions 1990m x 2380m (78 mils x 94 mils) thickness: 483m 25m (19 mils 1 mil) interface materials glassivation type: nitrox thickness: 15k? top metallization type: alcu (99.5%/0.5%) thickness: 30k? backside finish silicon assembly related information substrate potential floating additional information worst case current density <2 x 10 5 a/cm 2 process dielectrically isolated advanced bipolar technology- pr40 metallization mask layout gnd pwr comp vs dnc dnc dnc vout sense vout force trim (see note 11 , table 3 ) gnd quiet
isl71091seh20 14 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsidiaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8632.2 march 17, 2016 for additional products, see www.intersil.com/en/products.html submit document feedback table 3. die layout x-y coordinates pad name pad number x (m) y (m) bond wires per pad ( note 12 ) gnd pwr 1 1 -436 1 gnd quiet 2 0 0 1 comp 3 -15 831 1 vs 4 -17 1018 1 dnc 5 dnc 6 dnc 7 vout sense 8 1633 786 1 vout force 9 1640 -436 1 trim 10 1505 -436 1 notes: 11. origin of coordinates is the centroid of gnd quiet. 12. bond wire size is 1 mil.
isl71091seh20 15 fn8632.2 march 17, 2016 submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related docu mentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also available from our website at www.intersil.com/support. revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please go to web to make sure you have the latest revision. date revision change march 17, 2016 fn8632.2 -updated related literature docume nt titles to match titles on the actual documents. -added table 1 on page 2. -on page 5: -changed electrical specification for flatpack note from: ?boldface limits apply over the operating temperature range, -55c to +125c and radiation.? to : ?boldface limits apply after radiation at +25c or across the operating temperature range, -55c to +1 25c without radiation, unless otherwise specified. -for parameters v oa (rows 2, 3, 4) in electrical specifications for flatpack table in the test conditions column changed from: ?note 10", to: ?note 9?. -removed reference to tb493 as this is not applicable to hermetic packages. -on page 6: -changed electrical specification for die note from: ?boldface limits apply over the operating temperature range, -55c to +125c and radiation.? to: ?boldface limits apply after radiation at +25c or across the operating temperature range, -55c to +1 25c without radiation, unless otherwise specified. -for parameter v oa post rad (row 4) in electrical specifications for die table changed description from: ?v out accuracy at t a = -55c to +125c, post radiation?, to: ?v out accuracy at t a = +25c, post radiation?. -updated pod k8.a to the latest revision changes are as follows: -modified note 2 by adding the words ?...in addition to or instead of...?. july 11, 2014 fn8632.1 page 1 - changed title from: ?radiation ha rdened ultra low noise, precision voltage reference? to: ?2.048v radiation hardened ultra low noise, precision voltage reference? may 28, 2014 fn8632.0 initial release.
isl71091seh20 16 fn8632.2 march 17, 2016 submit document feedback package outline drawing k8.a 8 lead ceramic metal seal flatpack package rev 4, 12/14 lead finish side view top view -d- -c- 0.265 (6.75) 0.110 (2.79) 0.026 (0.66) 0.265 (6.73) seating and 0.180 (4.57) 0.03 (0.76) min base plane -h- 0.009 (0.23) 0.005 (0.13) pin no. 1 id area 0.050 (1.27 bsc) 0.022 (0.56) 0.015 (0.38) min 0.245 (6.22) 0.087 (2.21) 0.170 (4.32) 0.370 (9.40) 0.325 (8.26) 0.004 (0.10) 0.245 (6.22) 1. adjacent to pin one and shall be located within the shaded area shown. the manufacturers identification shall not be used as a pin on e identification mark. alternately, a tab may be used to identify pin one. 2. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the finished lead surfaces, when so lder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads . 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0. 038mm) maximum when solder dip lead finish is applied. 7. 8. notes: 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 dimensioning and tolerancing per ansi y14.5m - 1982. controlling dimension: inch. index area: a notch or a pin one identification mark shall be l ocated if a pin one identification mark is used in addition to or inst ead of a tab, measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materi als dimension shall be measured at the point of exit (beyond the section a-a base metal 0.007 (0.18) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38) 0.036 (0.92) the limits of the tab dimension do not apply.

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